Monday, 8 June 2015

An FPGA dev board on breadboard

In the end I ordered some additional PLCC sockets from the UK and was surprised and happy that they arrived in only a couple of days.

Soldering the sockets was easy, considering the board lacks a solder mask. Possibly the use of some liquid flux helped. I was happy with the result although it is not quite perfect:


The next step was to attach the adapter to the breadboard. This is the setup in the initial configuration, with the FPGA in its 84 pin adapter, flash in its 20 pin adapter, 10 pin IDC socket for the JTAG connection and power adapter. At this stage the FPGA was not wired to receive the design from the flash:


The ribbon connector was for the next step. The first thing to do was to verify that I could program both the flash and the FPGA. After fixing a missing connection everything was fine; the FPGA accepted the design.

The missing connection was the TRST JTAG line. Some programmers support this, some do not. If it is missing it needs to be tied high.

The next step was to verify that the FPGA would implement a design that was programmed into it. The simplest design worth testing is a counter. Just to make it slightly more interesting I made it an up down counter with reset. The counter is clocked via an "external" counter which divides down the 8Mhz can oscillator to make the 8 bit counter's output changes perceptible. To obtain a 1Hz output from a 8Mhz input, a 23 bit counter is required. The updated breadboard looks like the following:


You can see the can oscillator, two buttons (one for reset and one to make the counter count down) and the 8 LEDs along the top row of the breadboard. The counter worked well, and the VHDL is so trivial it is not worth showing. It was a big relief to see this working. Another nice thing was how quickly the design was downloaded onto the FPGA: only a few milliseconds were needed. The other thing worth noting is that it was still possible to program the flash in this configuration without removing any wires. Indeed, whilst the flash was being updated, the FPGA kept on going.

Of course when power was removed the FPGA lost the design. So the next step was to hook up the serial programming bus between the flash and the FPGA. After a few misswirings were corrected this worked well. I need to get the Analyser on the breadboard to properly time it out, but it appears to, again, take only a few milliseconds after power on for the counter outputs to show at the LEDs. Looking at the breadboard now it is easy to think that this is a lot of components and wires to do the same thing that I had the XC9572 doing a year or so ago. The difference is that the FPGA can hold a design that is many times more complex.

For fun, I also made a 16 bit up down counter with seven segment display. This was based on the previous 8 bit up down counter with display implemented on a CPLD. The breadboard looked like the following:


The four digits display is the common cathode type, so segments must be sourced current from the output pins connected to the segments. Individual digits are selected by setting the common cathodes to zero volts. This is the reverse of the two digit displays used in the eight bit counter, as well as my laminator controller board, described previously. If I was doing this properly I would use transistor drivers on the cathode pins, but I'm being lazy so instead current that lights the LEDs flows in and out of the FPGA directly.

I'm now in the process of setting up my 6809 computer again so I can attempt to link it to the FPGA. Doing this will allow me to verify that the two parts, manufactured about 30 years apart, will be able to interoperate. Mirroring my experiments with the XC5972 CPLD, I will make the hex display into an output latch. I will also try hooking up a buzzer to the FPGA, and implement an output register for producing tones from the buzzer etc.

But that has to wait until I have setup the Xilinx tools on a new VirtualBox Windows image. Since I've not touched the 6809 in quite a while, I need to re-flash the original non-DMA controller design on the XC95108 CPLD and modify the 6809 monitor to work without the IO board attached. It seems like it's been years since I touched the 6809 computer...

Tuesday, 2 June 2015

Breadboard power solution and the start of FPGA dev board version 2

When working with solderless breadboard, one of the concerns is how to power it. Ideally I would have a nice bench PSU but, being cheap, I makedo without one. In the past I have stumbled around with various solutions, including using the power pins on a USB serial breakout board, using an AVR programmer header just for the purpose of power, and my best solution so far: hacking the end off a USB cable and soldering some PCB pins to the power strands of the cable.

Using a 5V USB charger, such as the Apple iPad/iPhone device, is definitely a good starting point. These chargers are everywhere and can generally supply at least an Ampere, more then enough for my breadboard needs. The problem is attaching the "host" end to the breadboard. My solution is a simple one: a little PCB which contains a USB-B socket and some PCB header pins to connect the board to the breadboard.

For what it's worth, here is the schematic:


And here is the equally trivial PCB design. I did not bother to align the silk-screen, since I only need the copper artwork:


I made 3 of the little boards, attached together until etching, after which they were scored and broken apart. One board section didn't etch well, so was discarded. Of the remaining two, only one has been soldered up. Here it is attached to the breadboard:


It's a nice little device, I think. The switch makes it easy to reset microcontrollers on the breadboard, etc. The purpose of the screw terminals is to tap out the power rails to another board or device, if desired.

The above picture shows some other progress. Last week I received the parts from UTSource: 3 FLEX10K (PDF) FPGAs and 3 EPC2 (PDF) configuration flashes. As I mentioned in my previous post, the first task was to check that I could program the flash with the Altera programmer. To do this required a PLCC20 to DIP adapter (bought from eBay), the flash IC, a 10 pin IDC breadboard adapter (made up a year or more ago), the Altera programmer, and a means to power the breadboard (described above).

Fortunately programming the flash worked without a hitch. I even created a JTAG chain, consisting of two flashes, and both (or either) can be programmed from the Altera software with ease. This was a big relief after the issues I had with the FLEX6000, though obviously this is only a small step.

The step after this was to draw up a schematic for the FLEX10K dev board. I have abandoned the idea of making up this circuit on my own PCB, and instead have gone for the breadboard approach, with the FPGA in PLCC84 being attached to the breadboard via an adapter. Here is the schematic for the dev board, as it currently stands:


Since the circuit will be made up on breadboard this schematic serves only as a guide when plugging everything in. The most important part is the linkage between the configuration flash and the FPGA. Note that this circuit shows the flash and the FPGA in a JTAG chain. I'm very keen to see how this will work in practise. Hopefully it will let me either program the flash (which will then send the configuration to the FPGA at power-on), or program the FPGA, in which case the configuration will only be implemented by the FPGA so long as it is powered. This will be useful in testing, since it should be a quicker way to see changes implemented in the FPGA, but in a final design is probably not that useful.

You can see there is no AVR this time. Instead an oscillator can is used to provide a test signal. I happen to have one laying around rated at 8MHz, so that will be the frequency input to one of the dedicated clockpins on the FPGA. This can then be divided down as desired. To test inputs and outputs, buttons and LEDs are also included. More complex stuff can be done via other ICs attached to the breadboard. One of my ideas is to use some seven segment displays to replicate the first programmable logic circuit I made on the XC9572 CPLD, that of the two hex digit up and down counter. Another thing I'm very keen to do is to see if I can attach the FPGA to my 6809 computer, since the eventual aim of all this is to include an FPGA (or two) as a critical part of my next 6809-based micro.

The next step, then, was to make up the PLCC84 to DIP84 adapter. This is a huge adapter, even bigger then the shrink DIP64 adapter I made up for the V9958. It requires 42 pins along the longer edge, almost the length of a breadboard slab. Here is the PCB design (a schematic is pointless here):


The width is the same as the shrink DIP64 adapter. You can see it provides barely enough room to route the traces to the PLCC84 adapter. I'm not currently able to finish this part, since I have no more PLCC84 sockets at the moment.

I was very pleased with the toner transfer of this adapter board:


And the etch went really well too:


After that it needed to be drilled out. I think I am very slowly getting the hang of drilling:


So I have to wait before continuing with the adapter build to receive the PLCC84 sockets. I have ordered 10, but since they are coming from China, I'm not expecting them for a few weeks.

In the meantime I will start on the VHDL coding for the test designs to run in the FPGA...